1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices providing reduced probabilities of erroneously reading data from memory cells.
2. Description of the Background Art
A non-volatile semiconductor memory device having a memory cell in the form of a transistor having a threshold voltage varying as a stored data level varies has its data read via a so-called discharging read circuit, a circuit through current detection, and the like.
For example, when the discharging read circuit is used, a memory cell has its content read, as follows: the time when a memory cell hardly passes an electric current as its content is read is the time when a low level is read. By contrast, the time when a high level is read is the time when a memory cell capable of passing an electric current larger than that of a saturation range of a transistor operating as an electric current source connected to a node subjected to a decision between the high and low levels (note that hereinafter the transistor will be referred to as a xe2x80x9ccurrent source transistorxe2x80x9d), has its content read. The discharging read circuit can thus determine whether a memory cell has the voltage of the high level or that of the low level.
A conventional discharging read circuit, however, has used a current source transistor which has not necessarily been given consideration to operate in an appropriate range, so that data may be read erroneously. More specifically, when the low level is read by the conventional discharging read circuit, a data line may have noise thereon or charge-share may be introduced so that the node subjected to a decision between the high and low levels may have a voltage drop to permit the current source transistor to supply an electric current smaller than the transistor""s saturation current, when the current source transistor operates in a linear range and data may thus be read erroneously.
FIG. 11 shows a configuration of a conventional discharging read circuit. As shown in FIG. 11, the conventional discharging read circuit, i.e., a non-volatile semiconductor memory device 106 includes a memory cell array 1 having a plurality of memory cells (not shown), an n-channel MOS transistor NM1 operative in a data read in response to a clock signal CNT to electrically couple nodes N3 and N4 together, a p-channel MOS transistor Tr15 provided between a power supply voltage Vcc and n-channel MOS transistor NM1 and acting as a current source transistor, and an inversion circuit 3 having as an input a connection node connecting p- and n-channel MOS transistors Tr15 and NM1 together to receive, invert and output a voltage level of an input signal.
Memory cell array 1 includes a word line and a bit line, and a word line decoder and a bit line decoder (not shown) for selecting a single memory cell from the plurality of memory cells. By way example, p-channel MOS transistor Tr15 has a threshold voltage of 0.6V and inversion circuit 3 has a threshold voltage of 1.5V for the sake of illustration.
N-channel MOS transistor NM1 is connected to memory cell array 1 through a node N4. P-channel MOS transistor Tr15, constantly supplying a current, typically has its gate connected to a ground voltage GND.
Node N3 is designed to be sufficiently short to be hardly affected by noise. By contrast, in general, node N4, providing a connection between n-channel MOS transistor NM1 and memory cell array 1, would inevitably be sufficiently longer than node N3. In nodes N3 and N4 there exist parasitic capacitances C2 and C1, respectively, and there exist a relationship C1 greater than C2. Power supply voltage Vcc is set to be 3V for the sake of illustration.
FIG. 12 represents a characteristics curve T1a representing characteristics of p-channel MOS transistor Tr15 for a value k of 1.2 xcexcA/V2. Value k indicates how readily/hardly p-channel MOS transistor Tr15 passes an electric current. In the figure, the vertical axis represents the electric current passed by p-channel MOS transistor Tr15 and the horizontal axis represents the voltage of node N3.
It is understood from the FIG. 12 curve T1a that p-channel MOS transistor Tr15 in a saturation range passes a current (a saturation current) having a value of 7.2 xcexcA. Furthermore, for curve T1a, p-channel MOS transistor Tr15 for a voltage smaller than 0.6V operates in the saturation range and for a voltage larger than 0.6V operates in a linear range.
Reference will now be made to FIGS. 11 and 12 to describe how non-volatile semiconductor memory device 106 operates when the high and low levels are read therefrom. When data is not read, node N3 has a voltage of 3V.
In reading data of the high level, a memory cell selected from the plurality of memory cells of memory cell array 1 (hereinafter referred to as a selected memory cell) is by way example capable of passing a maximal current of 10 xcexcA for the sake of illustration. Whether an output OUT is the high or low level is determined as follows: it has the high level when node N3 has a voltage smaller than the threshold voltage of inversion circuit 3, and it has the low level when node N3 has a voltage larger than the threshold voltage of inversion circuit 3.
In a data read, with p-channel MOS transistor Tr15 having a saturation current of 7.2 xcexcA, a selected memory cell can pass a larger amount of current than p-channel MOS transistor Tr15. As such, node N3 subjected to a decision between the high and low levels has a voltage drop substantially to 0V.
Thus the node N3 voltage is smaller than the inversion circuit""s threshold voltage of 1.5V and output OUT is set to be the high level.
Should node N4 have noise thereon or between nodes N3 and N4 charge-share be introduced and node N3 have a voltage dropping to be lower than the threshold voltage of 1.5V of inversion circuit 3, output OUT is set to be the high level and data is not read erroneously.
When the low level is read, a selected memory cell hardly passes a current, for the sake of illustration. By way of example, the selected memory cell provides a leak current of 0.1 xcexcA.
In a data read, the selected memory cell can only pass a current of 0.1 xcexcA. As such, node N3 subjected to a decision between the high and low levels hardly has a voltage drop. It substantially has a voltage of 3V.
If in this state for example node N4 has noise thereon or between nodes N3 and N4 charge-share is introduced and as a result node N3 has a voltage drop and instantly a current between 6 xcexcA and 7.2 xcexcA is passed allowing p-channel MOS transistor Tr15 to operate in the linear range, then node N3 has a voltage reduced to be smaller than the threshold voltage of 1.5V of inversion circuit 3 and despite that low-level data should be read, output OUT is set to be the high level and data would be read erroneously.
Thus in the conventional non-volatile semiconductor memory device a current source transistor""s appropriate gate voltage level has not particularly been considered. As a result, when a node subjected to a decision between the high and low levels has a voltage falling within a range of no more than a threshold voltage, the current source transistor tends to operate in a linear range. As such, in reading the low level when charge-share, noise on a data line, or the like causes an electric current smaller than the current source transistor""s saturation current to flow, a node subjected to a decision with respect to voltage can have a voltage of no more than the threshold voltage. Because of such a phenomenon, the conventional non-volatile semiconductor memory device has a high possibility that data is read from a memory cell erroneously.
The present invention contemplates a nonvolatile semiconductor memory device preventing erroneous reading of data in reading the low level when noise on a data line, charge-share, or the like has an effect to allow a current source transistor to supply an electric current of no more than a saturation current.
In summary, the present invention includes a plurality of memory cells, a data line, a sense amplifier circuit and a first voltage setting circuit. The data line is electrically coupled with a single cell selected from the plurality of memory cells in a data read operation. The sense amplifier circuit detects a current of the data line in the data read operation. The sense amplifier circuit includes a first current source supplying the data line with a current in the data read operation. The first current source has a first internal node connected to the data line in the data read operation and a first transistor electrically coupled between the first internal node and a power supply voltage. The sense amplifier circuit further includes a first conversion circuit comparing a voltage of the first internal node with a first threshold voltage in the data read operation. The first voltage setting circuit sets a voltage of a gate of the first transistor to operate the first transistor in a saturation range when the first internal node has a voltage in a range of no more than the first threshold voltage.
A main advantage of the present invention lies in that it can implement a non-volatile semiconductor memory device capable of providing a reduced probability of erroneously reading data from a memory cell as a transistor operating as a current source in a sense amplifier circuit can be configured to operate in a saturation range if an internal node subjected to a decision between the high and low levels has a voltage falling within a range of no more than a threshold voltage.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.